Publications
The Design and Implementation of a Multi-Chip Power Module Layout Synthesis Tool
MSEE Thesis
Download PDFMLParest: Machine Learning based Parasitic Estimation for Custom Circuit Design
DAC Paper
Download PDFMulti-Objective Layout Optimization for Multi-Chip Power Modules considering Electrical Parasitics and Thermal Performance
IEEE COMPEL Paper
Download PDFMulti-Chip Power Module Fast Thermal Modeling for Layout Optimization
CAD and Applications Conference Paper
Download PDF